Hardware Spec for Developers
Hardware Spec for Developers
This document describes the hardware details to enable the user to do more experiment with the hardware.
FPGA Pin-out
The following is FPGA pin-out definitions. They are all 3.3V CMOS.
set_property PACKAGE_PIN V17 [get_ports {adc_dat_a_i[0]}]
set_property PACKAGE_PIN U17 [get_ports {adc_dat_a_i[1]}]
set_property PACKAGE_PIN Y17 [get_ports {adc_dat_a_i[2]}]
set_property PACKAGE_PIN W16 [get_ports {adc_dat_a_i[3]}]
set_property PACKAGE_PIN Y16 [get_ports {adc_dat_a_i[4]}]
set_property PACKAGE_PIN W15 [get_ports {adc_dat_a_i[5]}]
set_property PACKAGE_PIN W14 [get_ports {adc_dat_a_i[6]}]
set_property PACKAGE_PIN Y14 [get_ports {adc_dat_a_i[7]}]
set_property PACKAGE_PIN W13 [get_ports {adc_dat_a_i[8]}]
set_property PACKAGE_PIN V12 [get_ports {adc_dat_a_i[9]}]
set_property PACKAGE_PIN V13 [get_ports {adc_dat_a_i[10]}]
set_property PACKAGE_PIN T14 [get_ports {adc_dat_a_i[11]}]
set_property PACKAGE_PIN T15 [get_ports {adc_dat_a_i[12]}]
set_property PACKAGE_PIN V15 [get_ports {adc_dat_a_i[13]}]
set_property PACKAGE_PIN T16 [get_ports {adc_dat_a_i[14]}]
set_property PACKAGE_PIN V16 [get_ports {adc_dat_a_i[15]}]
set_property PACKAGE_PIN P20 [get_ports adc_ofl_i]
set_property PACKAGE_PIN K14 [get_ports adc_pga_o]
set_property PACKAGE_PIN J15 [get_ports adc_dith_o]
set_property PACKAGE_PIN U18 [get_ports adc_clk_p_i]
set_property PACKAGE_PIN U19 [get_ports adc_clk_n_i]
set_property PACKAGE_PIN K18 [get_ports pps_i]
set_property PACKAGE_PIN G17 [get_ports {antenna_o[0]}]
set_property PACKAGE_PIN G18 [get_ports {antenna_o[1]}]
set_property PACKAGE_PIN H16 [get_ports {antenna_o[2]}]
set_property PACKAGE_PIN H17 [get_ports {antenna_o[3]}]
set_property PACKAGE_PIN J18 [get_ports {antenna_o[4]}]
set_property PACKAGE_PIN H18 [get_ports {antenna_o[5]}]
set_property PACKAGE_PIN F16 [get_ports led_o]
CPU Devices
This section gives the detailed information regarding the chips connect to ARM CPU.
I2C Bus
There are two devices on I2C bus (i2c0). One is EEPROM and another is Si5351.
EEPROM - Addr: 0x50 EEPROM stores lots of important information. Strongly suggest don't touch it. If you really want to use it, please backup the content first and use uboot-util to update the content.
Si5351 - Addr: 0x60 Si5351 CLK0 is used as ADC clock as well as FPGA main clock. CLK2 is used for CLK out.
ATT chip
AD8370 provides tunable ATT on the RF path. The IO mapping is following:
AD8370_CLCK = 13
AD8370_LTCH = 12
AD8370_DATA = 11
Control IO
Two Additional GPIO is controlling RF signal path.
SWITCH_HF_VHF = 10
ENABLE_CLKOUT = 49